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? 20 13 semiconductor components industries, llc. publication order number: FAN3217/d october-2017, rev. 2 fan32 16 / fan32 17 dual 2 - a , high - speed , low - side gate drivers fan3216 / FAN3217 dual 2-a, high-speed, low-side gate drivers features ? industry-standard pinouts ? 4.5-v to 18-v operating range ? 3-a peak sink/source at v dd = 12 v ? 2.4-a sink / 1.6-a source at v out = 6 v ? inverting configuration (fan3 216 ) and non-inverting configuration (fan3 217 ) ? internal resistors turn driver off if no inputs ? 12 -ns / 9-ns typical rise/fall times (1 nf load) ? 20 -ns typical propagation delay time matched w ithin 1 ns to the other channel ? ttl input thresholds ? millerdrive? technology ? double current capability by paralleling channels ? standard soic-8 package ? rated from C 40c to +125c ambient ? automotive qualified to aec-q100 (f085 versions) applications ? sw itch-mode pow er supplies ? high-efficiency mosfet sw itching ? synchronous rectifier circuits ? dc- to -dc converters ? motor control ? automotive-qualified systems (f085 version s) description the fa n3216 and FAN3217 dual 2 a gate drivers are designed to drive n-channel enhancement- mode mosfets in low -side sw itching applications by providing high peak current pulses dur ing the short sw itching intervals. they are both available w ith ttl input thresholds. internal circuitry provides an under- voltage lockout function by holding the output low until the supply voltage is w ithin the operating range. in addition, the drivers feature matched internal propagation delays betw een a and b channels for applications requir ing dual gate drives w ith critical timing, such as synchronous rectifiers. this also enables connecting tw o drivers in parallel to effectively double the current capability driving a single mosfet. the fa n3216/17 drivers incorporate miller drive? architecture for the final output stage. this bipolar- mosfet combination provides high current during the miller plateau stage of the mosfet turn-on / turn-off process to minimize sw itching loss, w hile providing rail- to -rail voltage sw ing and reverse current capability. the fan3216 offers two inverting drivers and the fa n3217 offers tw o non-inverting drivers. both are offered in a standard 8-pin soic package. figure 1. fan3 216 pin configuration figure 2. fan3 217 pin configuration 1 nc ina gnd nc vdd inb outa outb 2 3 4 8 6 5 a 7 b 1 nc vdd outa outb 2 3 4 8 6 5 7 a b nc ina gnd inb
www. onsemi .com 2 fan32 16 / fan32 17 2 dual 2 - a , high - speed , low - side gate drivers ordering information part number logic input threshold package packing method quantity per reel fan3216tmx dual inverting channels ttl soic - 8 tape & reel 2,500 fan3216tmx _f085 ( 1 ) dual inverting channels ttl soic - 8 tape & reel 2,500 FAN3217tmx dual non - inverting channels ttl soic - 8 tape & reel 2,500 FAN3217tmx _f085 ( 1 ) dual non - inverting channels ttl soic - 8 tape & reel 2,500 note: 1. qualified to aec - q100 package outlines figure 3. soic - 8 (top view ) thermal characteristics ( 2 ) package ? ? ? ? ? ? ? ? ? 2 3 8 6 1 4 7 5
www. onsemi .com 3 fan32 16 / fan32 17 2 dual 2 - a , high - speed , low - side gate drivers pin configurations figure 4. fan3216 figure 5. FAN3217 pin definitions pin name pin description 1 nc no connect. this pin can be grounded or left floating. 2 ina input to channel a . 3 gnd ground . common ground reference for input and output circuits. 4 inb input to channel b . 5 (fan3216) gate drive output b (inverted from the input): held low unless required input is present and v dd is above uvlo threshold. 5 (FAN3217) outb gate drive output b : held low unless required input(s) are present and v dd is above uvlo threshold. 6 vdd supply voltage . provides pow er to the ic. 7 (fan3216) gate drive output a (inverted from the input): held low unless required input is present and v dd is above uvlo threshold. 7 (FAN3217) outa gate drive output a : held low unless required input(s) are present and v dd is above uvlo threshold. 8 nc no connect. this pin can be grounded or left floating. output logic fan3216 (x=a or b) FAN3217 (x=a or b) inx inx outx 0 1 0 ( 8 ) 0 1 ( 8 ) 0 1 1 note: 8. default input signal if no external connection is made . 1 n c i n a g n d n c v d d i n b o u t a o u t b 2 3 4 8 6 5 a 7 b 1 n c v d d o u t a o u t b 2 3 4 8 6 5 7 a b n c i n a g n d i n b outb outa outx
www. onsemi .com 4 fan32 16 / fan32 17 2 dual 2 - a , high - speed , low - side gate drivers block diagrams figure 6. fan3216 block diagram figure 7. FAN3217 block diagram 6 v d d 7 o u t a v d d _ o k 5 i n a 2 n c 1 g n d 3 u v l o 8 n c i n b 4 o u t b 1 0 0 k ? ? ? ? 6 v d d 7 o u t a v d d _ o k 5 i n a 2 n c 1 g n d 3 u v l o 8 n c i n b 4 o u t b 1 0 0 k ? ? ? ?
www. onsemi .com 5 fan32 16 / fan32 17 2 dual 2 - a , high - speed , low - side gate drivers absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition , extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd vdd to pgnd - 0.3 20.0 v v in ina and inb to gnd gnd - 0.3 v dd + 0.3 v v out outa and outb to gnd gnd - 0.3 v dd + 0.3 v t l lead soldering temperature (10 seconds) +260 oc t j junction temperature - 55 +150 oc t stg storage temperature - 65 +150 oc recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet spec ifications. on semiconductor does not recommend excee ding them or designing to absolute maximum ratings. symbol parameter min. max. unit v dd supply voltage range 4.5 18.0 v v in input voltage ina and inb 0 v dd v t a operating ambient temperature - 40 +125 oc
www. onsemi .com 6 fan32 16 / fan32 17 2 dual 2 - a , high - speed , low - side gate drivers electrical characteristics unless otherw ise noted, v dd =12 v , t j = - 40c to + 12 5c. currents are defined as positive into the device and negative out of the device. symbol parameter conditions min. typ. max. unit supply v dd operating range 4.5 18.0 v i dd supply current, inputs not connected 0.7 5 1.20 ma v on turn - on voltage ina= v dd , inb = 0 v 3. 4 5 3.9 0 4.3 5 v v off turn - off voltage ina= v dd , inb = 0 v 3.25 3.70 4.15 v fan3 216 tmx_f085, fan3 217 tmx_f085 (automotive - qualified versions) v on turn - on voltage ( 11 ) ina= v dd , inb = 0 v 3.4 0 3.90 4. 60 v v off turn - off voltage ( 11 ) ina= v dd , inb=0 v 3.2 0 3.70 4. 30 v inputs v il_t inx logic low threshold 0.8 1.2 v v ih_t inx logic high threshold 1.6 2.0 v v hys_t ttl logic hysteresis voltage 0.2 0.4 0.8 v fan3 216 tmx, fan3 217 tmx i i n + non - inverting input current in from 0 to v dd - 1. 0 175 a i i n - inverting input current in from 0 to v dd - 175.0 1. 0 a fan3 216 tmx_f085, fan3 217 tmx_f085 (automotive - qualified versions) i i nx_t non - inverting input current ( 11 ) in = 0 v - 1. 5 1.5 a i i nx_t non - inverting input current ( 11 ) in = v dd 90 120 175.0 a i i nx_t inverting input current ( 11 ) in = 0 v - 175.0 - 120 - 90 a i i nx_t inverting input current ( 11 ) in = v dd - 1. 5 1.5 a output s i sink out current, mid - voltage, sinking ( 9 ) outx at v dd /2, c load =0.22 f, f=1 khz 2.4 a i source out current, mid - voltage, sourcing ( 9 ) outx at v dd /2, c load =0.1 f, f=1 khz - 1.6 a i pk_sink out current, peak, sinking ( 9 ) c load =0.1 f, f=1 khz 3 a i pk_source out current, peak, sourcing ( 9 ) c load = 0.1 f, f=1 khz - 3 a t rise output rise time ( 10 ) c load =1000 pf 12 22 ns t fall output fall time ( 10 ) c load =1000 pf 9 17 ns t d1 , t d2 output propagation delay, ttl inputs ( 10 ) 0 5 v in , 1v/ns slew rate 10 19 34 ns propagation matching betw een channels ina=inb, outa and outb at 50% point 1 2 ns i rvs output reverse current withstand ( 9 ) 500 ma continued on the following page
www. onsemi .com 7 fan32 16 / fan32 17 2 dual 2 - a , high - speed , low - side gate drivers electrical characteristics (continued) unless otherw ise noted, v dd =12 v , t j = - 40c to + 12 5c. currents are defined as positive into the device and negative out of the device. symbol parameter conditions min. typ. max. unit output s (continued) fan3 216 tmx_f085, fan3 217 tmx_f085 (automotive - qualified versions) t d1 , t d2 output propagation delay, ttl inputs ( 11 ) 0 5 v in , 1 v/ns slew rate 4.5 19 .0 34 .0 ns propagation matching betw een channels ( 11 ) ina=inb, outa and outb at 50% point 2 4 ns v oh high level output voltage ( 11 ) v oh = v dd C see timing diagrams of figure 8 and figure 9 . 11. apply to only f085 version figure 8. non - inverting tim ing diagram figure 9. inverting tim ing diagram 9 0 % 1 0 % o u t p u t i n p u t t d 1 t d 2 t r i s e t f a l l v i n l v i n h 9 0 % 1 0 % o u t p u t t d 1 t d 2 t f a l l t r i s e v i n l v i n h i n p u t
www. onsemi .com 8 fan32 16 / fan32 17 2 dual 2 - a , high - speed , low - side gate drivers typical performance characteristics typical characteristics are provided at t a =25c and v dd =12 v unless otherw ise noted. figure 10. i dd (static) vs. supply voltage ( 12 ) figure 11. i dd (static) vs. tem perature ( 12 ) figure 12. i dd (no - load) vs. frequency figure 13. i dd (1 nf load) vs. frequency figure 14. input thresholds vs. supply voltage figure 15. input thresholds vs. tem perature
www. onsemi .com 9 fan32 16 / fan32 17 2 dual 2 - a , high - speed , low - side gate drivers typical performance characteristics typical characteristics are provided at t a =25c and v dd =12 v unless otherw ise noted. figure 16. uvlo threshold vs. tem perature figure 17. propagation delay vs. supply voltage figure 18. propagation delay vs. supply voltage figure 19. propagation delays vs. tem perature figure 20. propagation delays vs. tem perature
www. onsemi .com 10 fan32 16 / fan32 17 2 dual 2 - a , high - speed , low - side gate drivers typical performance characteristics typical characteristics are provided at t a =25c and v dd =12 v unless otherw ise noted. figure 21. fall tim e vs. supply voltage figure 22. rise tim e vs. supply voltage figure 23. rise and fall tim es vs. tem perature figure 24. rise/fall waveform s w ith 2.2 nf load figure 25. rise/fall waveform s w ith 10 nf load
www. onsemi .com 11 fan32 16 / fan32 17 2 dual 2 - a , high - speed , low - side gate drivers typical performance characteristics typical characteristics are provided at t a =25c and v dd =12 v unless otherw ise noted. figure 26. quasi - static source current w ith v dd =12 v ( 13 ) figure 27. quasi - static sink current w ith v dd =12 v ( 13 ) figure 28. quasi - static source current w it h v dd =8 v ( 13 ) figure 29. quasi - static sink current w ith v dd =8 v ( 13 ) notes: 12. for any inverting inputs pulled low , non - inverting inputs pulled high, or outputs driven high; static idd increases by the current flow ing through the corresponding pull - up/dow n resistor show n in figure 6 and figure 7 . 13. the initial spik e in each current w aveform is a measurement artifact caused by the stray inductance of the current - measurement loop. test circuit figure 30. quasi - static i out / v out test circuit 1 2 0 f a l . e l . v d d v o u t 1 f c e r a m i c 4 . 7 f c e r a m i c c l o a d 0 . 1 f i o u t i n 1 k h z c u r r e n t p r o b e l e c r o y a p 0 1 5
www. onsemi .com 12 fan32 16 / fan32 17 2 dual 2 - a , high - speed , low - side gate drivers applications information input thresholds the fan3216 and the FAN3217 drivers consist of tw o identical channels that may be used independently at rated current or connected in parallel to double the individual current capacity. the i nput thresholds meet industry - standard ttl - logic thresholds independent of the v dd voltage, and there is a hysteresis voltage of approximately 0.4 v. these levels per mit the inputs to be driven from a range of input logic s ignal levels for w hich a voltage over 2 v is considered logic high. the driving signal for the ttl inputs should have fast rising and falling edges w ith a slew rate of 6 v/s or faster, so a rise time from 0 to 3.3 v should be 550 ns or less. with reduced slew rate, circuit noise could ca use the driver input voltage to exceed the hysteresis voltage and retrigger the dr iver input, causing erratic operation. static supply current in the i dd (static) typical performance characteristics show n in figure 10 and figure 11 , each curve is produced w ith both inputs floating and both outputs low to indicate th e low est static i dd current. for other states, additional current flows through the 100k ? (see figure 6 and figure 7 ) . in these cases, the actual static i dd current is the value obtained from the curves plus this additional current. m loohu'ulyh?*dwh'ulyh7hfkqrorj\ fa n3216 and fa n3217 gate drivers incorporate the 0loohu 'ulyh? dufklwhfwxuh vkrz q lq figure 31 . for the output stage, a combination of bipolar and mos devices provide large currents over a w ide range of supply voltage and temperature variations. the bipolar devices carry the bulk of th e current as out sw ings betw een 1/3 to 2/3 v dd and the mos devices pull the output to the high or low rail. 7kh sxusrvh ri wkh 0loohu 'ulyh? dufklwhfwxuh lv wr speed up sw itching by providing high current during the miller plateau region w hen the gate - drain capacitance of the mosfet is being charged or discharged as part of the turn - on / turn - off process. for applications w ith zero voltage sw itching during the mosfet turn - on or turn - off interval, the driver supplies high peak current for fast sw itching even though the miller plateau is not present. this situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the mosfet is sw itched on. the output pin slew rate is determined by v dd voltage and the loa d on the output. it is not user adjustable, but a series resistor can be added if a slow er rise or fall time at the mosfet gate is needed. figure 31. 0loohu'ulyh?2xwsxw$ufklwhfwxuh under - voltage lockout the fan321x startup logic is opt imized to drive ground - referenced n - channel mosfets w ith an under - voltage lockout ( uvlo) function to ensure that the ic starts up in an orderly fashion. when v dd is rising, yet below the 3.9 v operational level, this circuit holds the output low, regardles s of the status of the input pins. after the part is active, the supply voltage must drop 0.2 v before the part shuts dow n. this hysteresis helps prevent chatter w hen low v dd supply voltages have noise from the pow er sw itching. this configuration is not su itable for driving high - side p - channel mosfets because the low output voltage of the driver w ould turn the p - channel mosfet on w ith v dd below 3.9 v. v dd bypass capacitor guidelines to enable this ic to turn a device on quickly, a local high - frequency bypa ss capacitor, c byp , w ith low esr and esl should be connected betw een the vdd and gnd pins w ith minimal trace length. this capacitor is in addition to bulk electrolytic capacitance of 10 f to 47 f commonly found on driver and controller bias circuits. a typical criterion for choosing the value of c byp is to keep the ripple voltage on the v dd vxsso\wr?7klv lvriwhqdfklhyhgz lwkdydoxh?wlphvwkhhtxlydohqw load capacitance c eqv , defined here as q gate /v dd . ceramic capacitors of 0.1 f to 1 f o r larger are common choices, as are dielectrics, such as x5r and x7r, w ith good temperature characteristics and high pulse current capability. if circuit noise affects normal operation, the value of c byp may be increased, to 50 - 100 times the c eqv , or c byp may be split into tw o capacitors. one should be a larger value, based on equivalent load capacitance, and the other a s maller value, such as 1 - 10 nf mounted closest to the vdd and gnd pins to carry the higher - frequency components of the current pulses. th e bypass capacitor must provide the pulsed current from both of the driver channels and, if the drivers are sw itching simultaneously, the combined peak current sourced from the c byp w ould be tw ice as large as w hen a single channel is sw itching. i n p u t s t a g e v d d v o u t
www. onsemi .com 13 layout and connection guidelines the fa n3216 and FAN3217 gate dr ivers incorporate fast - reacting input circuits, short propagation delays, and pow erful output stages capable of delivering current peaks over 2 a to facili tate voltage transition times from under 10 ns to over 150 ns. the follow ing layout and connection guidelines are strongly recommended: ? keep high - current output and pow er ground paths separate from logic input signals and signal ground paths. this is espec ially critical for ttl - level logic thresholds at driver input pins. ? keep the driver as close to the load as possible to minimize the length of high - current traces. this reduces the ser ies inductance to improve high - speed sw itching, w hile reducing the loop area that can radiate emi to the driver inputs and surrounding circuitry. ? if the inputs to a channel are not externally connected, the internal 100 k ? p w m v d s v d d c b y p f a n 3 2 1 x p w m v d s v d d c b y p f a n 3 2 1 x
www. onsemi .com 14 fan32 16 / fan32 17 2 dual 2 - a , high - speed , low - side gate drivers operational waveforms at pow er - up, the driver output remains low until the v dd voltage reaches the turn - on threshold. the magnitude of the out pulses rises w ith v dd until steady - state v dd is reached. the non - inverting operation illustrated in figure 34 shows that the output remains low until the uvlo threshold is reached, then the output is in - phas e w ith the input. figure 34. non - inverting startup waveform s the inverting configuration of startup w aveforms are show n in figure 35 . with in+ t ied to v dd and the input signal applied to in , the out pulses are inverted w ith respect to the input. at pow er - up, the inverted output remains low until the v dd voltage reaches the turn - on threshold, then it follow s the input w ith inverted phase. figure 35. inverting startup waveform s v d d i n + i n - o u t t u r n - o n t h r e s h o l d v d d i n + ( v d d ) i n - o u t t u r n - o n t h r e s h o l d
www. onsemi .com 15 fan32 16 / fan32 17 2 dual 2 - a , high - speed , low - side gate drivers thermal guidelines gate dr ivers used to sw itch mosfets and igbts at high frequencies can dissipate s ignificant amounts of pow er. it is important to deter mine the driver pow er dissipation and the resulting junction temperature in the application to ensure that the part is operating w ithin acceptable temperature limits. the total pow er dissipation in a gate dr iver is the sum of tw o components, p gate and p dynamic : p total = p ga te + p dynamic (1) gate driving loss: the most significant pow er loss results from supplying gate current (charge per unit time) to sw itch the load mosfet on and off at the sw itching frequency. the pow er dissipation that results from dr iving a mosfet at a s pecified gate - source voltage, v gs , w ith gate charge, q g , at sw itching frequency, f sw , is determined by: p gate = q g ?9 gs ? f sw ?q (2) w here n is the number of driver channels in use (1 or 2). dynamic pr e - dr ive / shoot - through current: a pow er loss resul ting from internal current consumption under dynamic operating conditions, including pin pull - up / pull - dow n resistors, can be obtained using the graphs in typical performance characteristics to deter mine the current i dynamic draw n from v dd under actual op erating conditions: p dynamic = i dynamic ?9 dd ?q (3) once the pow er dissipated in the driver is deter mined, the driver junction rise w ith respect to circuit board can be evaluated using the follow ing ther mal equation, assuming ? ? ? ? ? ??
www. onsemi .com 16 fan32 16 / fan32 17 2 dual 2 - a , high - speed , low - side gate drivers typical application diagrams figure 36. forw ard converter w ith synchronous rectification figure 37. prim ary - s i de dual driver in a push - p ull converter figure 38. phase - s hifted full - b ridge w ith tw o gate drive transform ers (sim plified) v i n p w m 1 2 3 6 7 8 4 5 t i m i n g / i s o l a t i o n v o u t f a n 3 2 1 7 v b i a s v i n p w m a p w m b 1 2 3 6 7 8 4 5 v d d g n d o u t b o u t a f a n 3 2 1 7 p w m - a p w m - b 1 3 4 p w m - c p w m - d p h a s e s h i f t c o n t r o l l e r f a n 3 2 1 7 f a n 3 2 1 7 v i n v b i a s v b i a s 1 2 3 6 7 8 4 5 v d d g n d a b 2 6 7 8 5 v d d g n d a b
www. onsemi .com 17 fan32 16 / fan32 17 2 dual 2 - a , high - speed , low - side gate drivers table 1. related products type part num ber gate drive ( 14 ) (sink/src) input threshold logic package single 1 a fan3111c +1.1 a / - 0.9 a cmos single channel of dual - input/single - output sot23 - 5, mlp6 single 1 a fan3111e +1.1 a / - 0.9 a external ( 15 ) single non - inverting channel with external reference sot23 - 5, mlp6 single 2 a fan3100c +2.5 a / - 1.8 a cmos single channel of two - input/one - output sot23 - 5, mlp6 single 2 a fan3100t +2.5 a / - 1.8 a ttl single channel of two - input/one - output sot23 - 5, mlp6 single 2 a fan3180 +2.4 a / - 1.6 a ttl single non - inverting channel + 3.3 - v ldo sot23 - 5 dual 2 a fan3216t +2.4 a / - 1.6 a ttl dual inv erting channels soic8 dual 2 a FAN3217t +2.4 a / - 1.6 a ttl dual non - inv erting channels soic8 dual 2 a fan3226c +2.4 a / - 1.6 a cmos dual inverting channels + dual enable soic8, mlp8 dual 2 a fan3226t +2.4 a / - 1.6 a ttl dual inverting channels + dual enable soic8, mlp8 dual 2 a fan3227c +2.4 a / - 1.6 a cmos dual non - inverting channels + dual enable soic8, mlp8 dual 2 a fan3227t +2.4 a / - 1.6 a ttl dual non - inverting channels + dual enable soic8, mlp8 dual 2 a fan3228c +2.4 a / - 1.6 a cmos dual channels of two - input/one - output, pin config.1 soic8, mlp8 dual 2 a fan3228t +2.4 a / - 1.6 a ttl dual channels of two - input/one - output, pin config.1 soic8, mlp8 dual 2 a fan3229c +2.4 a / - 1.6 a cmos dual channels of two - input/one - output, pin config.2 soic8, mlp8 dual 2 a fan3229t +2.4 a / - 1.6 a ttl dual channels of two - input/one - output, pin config.2 soic8, mlp8 dual 2 a fan3268t +2.4 a / - 1.6 a ttl 20 v non - inverting channel (nmos) and inverting channel (pmos) + dual enables soic8 dual 2 a fan3278t +2.4 a / - 1.6 a ttl 30 v non - inverting channel (nmos) and inverting channel (pmos) + dual enables soic8 dual 4 a fan3213t +2.5 a / - 1.8 a ttl dual inverting channels soic8 dual 4 a fan3214t +2.5 a / - 1.8 a ttl dual non - inverting channels soic8 dual 4 a fan3223c +4.3 a / - 2.8 a cmos dual inverting channels + dual enable soic8, mlp8 dual 4 a fan3223t +4.3 a / - 2.8 a ttl dual inverting channels + dual enable soic8, mlp8 dual 4 a fan3224c +4.3 a / - 2.8 a cmos dual non - inverting channels + dual enable soic8, mlp8 dual 4 a fan3224t +4.3 a / - 2.8 a ttl dual non - inverting channels + dual enable soic8, mlp8 dual 4 a fan3225c +4.3 a / - 2.8 a cmos dual channels of two - input/one - output soic8, mlp8 dual 4 a fan3225t +4.3 a / - 2.8 a ttl dual channels of two - input/one - output soic8, mlp8 single 9 a fan3121c +9.7 a / - 7.1 a cmos single inverting channel + enable soic8, mlp8 single 9 a fan3121t +9.7 a / - 7.1 a ttl single inverting channel + enable soic8, mlp8 single 9 a fan3122t +9.7 a / - 7.1 a cmos single non - inverting channel + enable soic8, mlp8 single 9 a fan3122c +9.7 a / - 7.1 a ttl single non - inverting channel + enable soic8, mlp8 dual 12 a fan3240 +12.0 a ttl dual - coil relay driver, timing config. 0 soic8 dual 12 a fan3241 +12.0 a ttl dual - coil relay driver, timing config. 1 soic8 notes: 14. typical currents w ith ou tx at 6 v and v dd = 12 v. 15. thresholds proportional to an externally supplied reference voltage.
www. onsemi .com 18 fan32 16 / fan32 17 2 dual 2 - a , high - speed , low - side gate drivers ph ys ical dimensions figure 39. 8 - lead sm all outline integrated circuit ( soic ) package drawings are provided as a service to customers considering on semiconductor components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact on semiconductor representative to verify or obtain the most recent revision. package specifications do not expand the terms of on semiconductor s worldwide terms and conditions, specifically the warranty therein, which covers on semiconductor products. \ 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m b a 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge
www. onsemi .com 19 fan32 16 / fan32 17 2 dual 2 - a , high - speed , low - side gate drivers on semiconductor and the on semiconductor logo are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries in the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a olvwlqjri216hplfrqgxfwru?vsurgxfwsdwh nt coverage may be accessed at www.onsemi.com/site/pdf/patent - marking.pdf. on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regard ing the suit ability of its products for any particular purpose, nor does on semiconductor assume any liability arising out of the application or use of any product or ci rcuit, and specifically disclaims any and all liability, including without limitation special, cons equential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications informa tion provided by 216hplfrqgxfwru37\slfdosdudphwhuvzklfkpd\ehsurylghglq216hplfrqgxfwrugdwdvkhhwvdqgruvshflilfdwlrqvfdqdqggr vary in different applications and dfwxdoshuirupdqfhpd\ydu\ryhuwlph$oorshudwlqjsdudphwhuvlqfoxglqj37 \slfdovpxvwehydolgdwhgiruhdfkfxvwrphudssolfdwlrqe\fxvwrphu?vwhfkqlfdoh[shuwv on semiconductor does not convey any license under its patent rights nor the rights of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or simi lar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distr ibutors harmless against all claims, costs, damages, and expe nses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated w ith such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or man ufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 - 675 - 2175 or 800 - 344 - 3860 toll free usa/canada fax : 303 - 675 - 2176 or 800 - 344 - 3867 toll free usa/canada email : orderlit@onsemi.com n. amer ican t echnical support : 800 - 282 - 9855 toll free usa/canada. eur ope, middle east and afr ica technical support : phone: 421 33 790 2910 japan customer focus center phone: 81 - 3 - 5817 - 1050 on semiconductor website : www.onsemi.com or der literature : http://www.onsem i.com/orderlit for additional information, please contact your local sales representative

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